Hardware-Software Co-Design Course

RISC-V Hardware-Software co-design

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Course Objective

This summer school is designed to provide students, researchers, and early-career engineers with a practical understanding of RISC-V architecture and modern hardware–software co-design methodologies. Participants will learn how open-source RISC-V platforms enable the development of high-performance computing (HPC), AI acceleration, and embedded systems applications.

The program combines architectural concepts, software toolchains, firmware development, Linux system bring-up, and AI compiler technologies to equip participants with the skills required to build, optimize, and deploy applications on RISC-V and vector accelerator platforms. Through hands-on exercises and expert-led sessions, attendees will gain exposure to industry-relevant workflows used in next-generation computing systems.

Learning Outcomes

Upon successful completion of this summer school, participants will understand the fundamentals of RISC-V architecture, vector extensions, and accelerator-based computing platforms. They will gain practical knowledge of hardware–software co-design principles and system-level optimization techniques.

Participants will be able to work with RISC-V compiler toolchains, develop firmware for accelerator-enabled platforms, perform Linux bring-up on RISC-V systems, and understand modern AI compiler frameworks such as MLIR. They will also develop the ability to analyze performance, optimize workloads, and contribute to open-source hardware and software ecosystems.

Summer School Modules

Module 1: Introduction to RISC-V and Vector Accelerators

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1.1 Evolution of Open ISA Architectures

1.2 Fundamentals of RISC-V

1.3 RISC-V Instruction Set Architecture

1.4 Vector Processing Concepts

1.5 Introduction to Vector Accelerators

1.6 Applications in HPC and AI

Module 2: RISC-V Hardware–Software Co-Design Methodology

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2.1 Principles of Hardware–Software Co-Design

2.2 System Architecture Design Flow

2.3 Accelerator Integration Strategies

2.4 Performance and Resource Trade-offs

2.5 SoC-Level Design Considerations

2.6 Case Studies and Practical Examples

Module 3: Compiler Toolchains for RISC-V and Vector Accelerator Systems

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3.1 GCC and LLVM Toolchains

3.2 Cross-Compilation for RISC-V

3.3 Vector Extension Support

3.4 Optimization Techniques

3.5 Debugging and Profiling Tools

3.6 Building Accelerator-Aware Applications

Module 4: Firmware Development for RISC-V Vector Accelerator Platforms

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4.1 Embedded Software Fundamentals

4.2 Bare-Metal Programming

4.3 Firmware Architecture Design

4.4 Accelerator Control Interfaces

4.5 Driver Development Concepts

4.6 Performance Validation and Testing

Module 5: Linux System Bring-Up for RISC-V HPC Platforms

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5.1 Linux Boot Process on RISC-V

5.2 Device Trees and Platform Configuration

5.3 Kernel Customization

5.4 Driver Integration

5.5 Userspace Development Environment

5.6 HPC Platform Deployment

Module 6: AI Compiler Development and MLIR-Based Acceleration

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6.1 Introduction to AI Compilers

6.2 MLIR Fundamentals

6.3 Intermediate Representations and Optimizations

6.4 Accelerator-Aware Compilation

6.5 AI Workload Deployment Pipelines

6.6 Future Trends in AI Acceleration