Summer School on RISC-V Hardware–Software Co-Design

 

 

 

 

 

 

RISC-V Summer School poster

Quick Facts

  • Registration Deadline: 28 August 2026
  • Certificate: Awarded on full attendance and completion of practical activities
  • Lunch / Refreshments: Provided by CAID
  • Accommodation Complimentary shared accommodation for confirmed outstation participants, subject to availability.
  • Laptop: At least 8 GB RAM, with administrative access

Summer School on RISC-V Hardware–Software Co-Design

5–6 September 2026  |  Executive Hall, Namal University, Mianwali
Limited Seats – 30 Only
Register Now

Registration Fee

  • Professionals: PKR 40,000
  • Faculty Members: PKR 30,000
  • Students: PKR 5,000

Summer School Objective

This summer school provides students, researchers, faculty members, and early-career engineers with a practical understanding of RISC-V architecture, vector processing, and modern hardware–software co-design methodologies. Participants will explore how the open and extensible RISC-V ecosystem supports embedded systems, high-performance computing, and AI acceleration.

The program combines architectural concepts, accelerator integration, compiler toolchains, firmware development, Linux system bring-up, and MLIR-based AI compilation. Through expert-led lectures and guided practical sessions, participants will gain exposure to the workflows used to design, optimize, and deploy applications on RISC-V and vector-accelerator platforms.

Learning Outcomes

Upon completion of the summer school, participants will be able to:

  • Explain the fundamentals of the RISC-V ISA, vector processing, and accelerator-based computing.
  • Understand the major stages of hardware–software co-design, including accelerator integration, firmware control, compiler support, and Linux platform configuration.
  • Gain introductory practical experience in RISC-V cross-compilation, vector programming, accelerator communication, Linux bring-up, and MLIR-based compilation workflows.
Audience

Who Should Attend

The summer school is suitable for:

  • Undergraduate and graduate students
  • Researchers and academic faculty
  • Embedded-system developers and compiler engineers
  • Professionals interested in RISC-V, AI acceleration, and computer architecture
  • Early-career engineers in high-performance computing
Entry Requirements

Prerequisites

Participants should have:

  • Basic knowledge of C/C++
  • Basic familiarity with computer architecture and embedded systems
  • Familiarity with Linux is recommended

Prior experience with RISC-V or MLIR is helpful but not mandatory.

Laptop Requirement Bring a laptop with at least 8 GB RAM and administrator access. Software installation instructions will be shared with confirmed participants before the summer school.
Technical Environment

Tools and Platforms

  • RISC-V GCC and LLVM toolchains
  • QEMU simulator
  • RISC-V vector intrinsics
  • Linux kernel and device tree
  • MLIR and LLVM infrastructure
  • FPGA-based or simulated RISC-V accelerator platform
Applied Learning

Practical Sessions

Guided practical activities will include:

  • RISC-V GCC and LLVM cross-compilation
  • Basic RISC-V assembly and C programming
  • RVV intrinsic-based vector programming
  • Firmware control of an accelerator through MMIO
  • Device-tree configuration
  • Linux driver integration concepts
  • MLIR lowering of a simple matrix multiplication or AI kernel

Gallery

Two-Day Agenda & Session Topics

Day 1 – 5 September 2026

Opening Registration and Opening Remarks
Practical Cross-compilation & RVV intrinsic programming
Review Close of Day 1

Day 2 – 6 September 2026

Practical MLIR lowering demo & firmware/MMIO exercise
Closing Certificate distribution and closing ceremony

Lead Trainer

Dr. Tassadaq Hussain Cheema

Director, Centre for AI & Big Data (CAID)

Expertise Computer architecture, processor-based systems, and parallel programming.

Dr. Tassadaq Hussain is a computer architect with more than 20 years of national and international experience in computer architecture, parallel computing, embedded systems, and hardware–software co-design. He has led the development of processor architectures and software solutions for industrial applications and has extensive experience in research, technology development, project leadership, and professional training.

Registration Process

  1. Submit the form Complete the online registration form with the required details.
  2. Verification Places are assigned first-come, first-served after form and payment verification.
  3. Confirmation Successful applicants are notified through email or WhatsApp.
Open Registration Form