Summer School on RISC-V Hardware–Software Co-Design

CAID Summer School

Summer School on RISC-V Hardware–Software Co-Design

5–6 September 2026 · Executive Hall, Namal University, Mianwali
Register Now Limited Seats – 30 Only
RISC-V Summer School poster
Summer School

Objective and outcomes

This summer school provides students, researchers, faculty members, and early-career engineers with a practical understanding of RISC-V architecture, vector processing, and modern hardware–software co-design methodologies. Participants will explore how the open and extensible RISC-V ecosystem supports embedded systems, high-performance computing, and AI acceleration.

The program combines architectural concepts, accelerator integration, compiler toolchains, firmware development, Linux system bring-up, and MLIR-based AI compilation. Through expert-led lectures and guided practical sessions, participants will gain exposure to the workflows used to design, optimize, and deploy applications on RISC-V and vector-accelerator platforms.

  • 1

    Explain the fundamentals of the RISC-V ISA, vector processing, and accelerator-based computing.

  • 2

    Understand the major stages of hardware–software co-design, including accelerator integration, firmware control, compiler support, and Linux platform configuration.

  • 3

    Gain introductory practical experience in RISC-V cross-compilation, vector programming, accelerator communication, Linux bring-up, and MLIR-based compilation workflows.

Program

Who should attend and how to participate

Who Should Attend

The summer school is suitable for:

  • Undergraduate and graduate students
  • Researchers and academic faculty
  • Embedded-system developers and compiler engineers
  • Professionals interested in RISC-V, AI acceleration, and computer architecture
  • Early-career engineers in high-performance computing

Prerequisites

Participants should have:

  • Basic knowledge of C/C++
  • Basic familiarity with computer architecture and embedded systems
  • Familiarity with Linux is recommended

Prior experience with RISC-V or MLIR is helpful but not mandatory.

Laptop Requirement Bring a laptop with at least 8 GB RAM and administrator access. Software installation instructions will be shared with confirmed participants before the summer school.

Tools and Platforms

  • RISC-V GCC and LLVM toolchains
  • QEMU simulator
  • RISC-V vector intrinsics
  • Linux kernel and device tree
  • MLIR and LLVM infrastructure
  • FPGA-based or simulated RISC-V accelerator platform

Practical Sessions

Guided practical activities will include:

  • RISC-V GCC and LLVM cross-compilation
  • Basic RISC-V assembly and C programming
  • RVV intrinsic-based vector programming
  • Firmware control of an accelerator through MMIO
  • Device-tree configuration
  • Linux driver integration concepts
  • MLIR lowering of a simple matrix multiplication or AI kernel
Session Posters

Lectures & Hands-on Session

The lecture details, hands-on activities, and trainer information are provided in the posters below.

Day 1 Lecture 1 poster: Introduction to RISC-V and Vector Accelerators

Lecture 1: Introduction to RISC-V and Vector Accelerators

Day 1 Lecture 2 poster: RISC-V Hardware-Software Co-Design Methodology

Lecture 2: RISC-V Hardware–Software Co-Design Methodology

Day 1 Lecture 3 poster: RISC-V Vector Accelerator Design and System Integration

Lecture 3: RISC-V Vector Accelerator Design and System Integration

Day 1 Lecture 4 poster: RISC-V Vector Toolchains and Firmware Development

Lecture 4: RISC-V Vector Toolchains and Firmware Development

Day 1 Lecture 5 poster: Functional verification of RISC-V designs

Lecture 5: Functional Verification of RISC-V Designs

Day 2 Poster: AI and the Future of Work

AI and the Future of Work: What Will Change, What Won’t

Day 2 Lecture 6 poster: IREE, an MLIR based compiler

Lecture 6: IREE – An MLIR Based Compiler

Day 2 Lecture 7 poster: Bringing GNU/Linux to work with experimental RISC-V cores

Lecture 7: Bringing GNU/Linux to Work with Experimental RISC-V Cores

Day 2 Poster: AI Compilers and Llama.cpp for efficient inference of GenAI models on RISC-V Silicon

AI Compilers & Llama.cpp for GenAI Inference on RISC-V Silicon

Day 2 Poster: Certificate Distribution and Closing Ceremony

AI Compilers & Llama.cpp for GenAI Inference on RISC-V Silicon

Gallery

Event highlights

Agenda

Two-Day Agenda & Session Topics

Day 1 – 5 September 2026

OpeningRegistration and Opening Remarks · Coordinator
  • The rise of open ISAs, and what makes RISC-V different: a small base integer ISA plus modular, optional extensions
  • Vector processing fundamentals and the RISC-V Vector (RVV) extension
  • Vector accelerators: architecture, data movement, and where the speed-up actually comes from
  • Where RISC-V is being applied today across embedded, HPC, and AI workloads
  • Principles of hardware-software co-design and the system architecture design flow
  • Strategies for integrating an accelerator into a RISC-V system
  • Trading performance against area, power, and resource budgets
  • SoC-level design considerations, drawn out through worked case studies
  • RISC-V SoC architecture and the design of accelerator interfaces
  • Memory-mapped I/O and shared-memory communication between core and accelerator
  • Interrupt handling, DMA, and efficient movement of data
  • Integrating an accelerator onto an FPGA-based platform
  • Hands-on: Cross-compilation and RVV intrinsic programming
BreakLunch and Prayer Break
  • Set up GCC/LLVM RISC-V cross-compilation toolchains
  • Understand RVV compilation and vectorization
  • Develop bare-metal firmware and accelerator drivers
  • Apply accelerator-aware optimization techniques
  • Use debugging, profiling, and validation tools
  • Formal methods and testbenches for validating ISA compliance
  • Coverage-driven verification approaches for RISC-V processor designs
  • Industry tools and methodologies for comprehensive design verification and bug detection
CloseClose of Day 1 · Coordinator

Day 2 – 6 September 2026

  • How AI is transforming tasks, jobs, and industries
  • Automation, augmentation, and uniquely human capabilities
  • AI literacy, technical skills, critical thinking, creativity, and communication
  • How students can build careers through continuous learning and human–AI collaboration
  • MLIR-based end-to-end compiler and runtime and what it means
  • Model import from an HL framework (e.g. PyTorch) to MLIR, step by step
  • Lowering, optimization, scheduling, and hardware-specific code generation
  • Executing compiled models across CPUs, GPUs, RISC-V, and accelerators
  • The Linux boot process on RISC-V, from firmware through to user-space
  • Device trees and platform configuration
  • Kernel customization and driver integration
  • Standing up a user-space development environment for HPC deployment
  • Overview of compiler techniques that optimize GenAI model execution on RISC-V hardware
  • Key strategies for reducing latency, memory usage, and power consumption in edge deployment scenarios
  • Practical demonstration of running large language models efficiently on RISC-V-based systems
BreakLunch Break
ClosingCertificate Distribution and Closing Ceremony · Coordinator

Lead Trainer

Dr. Tassadaq Hussain Cheema

Director, Centre for AI & Big Data (CAID)

Expertise Computer architecture, processor-based systems, and parallel programming.

Dr. Tassadaq Hussain is a computer architect with more than 20 years of national and international experience in computer architecture, parallel computing, embedded systems, and hardware–software co-design. He has led the development of processor architectures and software solutions for industrial applications and has extensive experience in research, technology development, project leadership, and professional training.

Registration Process

  1. Submit the form Complete the online registration form with the required details.
  2. Verification Places are assigned first-come, first-served after form and payment verification.
  3. Confirmation Successful applicants are notified through email or WhatsApp.
Open Registration Form

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